The present disclosure relates to a design structure, and more specifically, to a design structure for a set of semiconductor fins with gate layers and an interconnect layer.
In some instances, semiconductor device technology nodes, such as 14 nanometer (nm), 20 nm, 22 nm, and other technology nodes can place various restrictions on semiconductor design. Further, in some instances, semiconductor manufacturing can result in “padding” structures. Padding structures can be semiconductor structures not made for function but as aids for patterning devices. In some instances, the area associated with padding can be significant, utilizing several percent of a silicon area on a die. Further, in some instances, the smaller the semiconductor device, the greater the number of padding (e.g. dummy devices) required on a die relative to number of functional devices.